EDN

Synplicity steps up synthesis competition with ASIC tool

SAN MATEO, Calif. — Synplicity Inc. is targeting the ASIC synthesis market after years of dominating FPGA synthesis with an announcement that it is co-developing with LSI Logic an ASIC physical ...
EDN

ASICs added to Synplicity’s synthesis line

San Mateo, Calif. – Already a player in FPGA synthesis, Synplicity Inc. will expand into ASIC physical synthesis this week with a tool that competes against offerings from Synopsys, Cadence and Magma.
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Design-Reuse

Synplicity and NEC Electronics Ink Physical Synthesis OEM Agreement for ISSP Structured ASICS

NEC Electronics Integrates Amplify-ISSP Software into its OpenCAD Design Environment for Use in ISSP Structured ASIC Designs SUNNYVALE, Calif. and KAWASAKI, Japan, — 24 May 2004 -- NEC Electronics ...
Design-Reuse

Cutting a fast path to semiconductors: With special synthesis and processing, algorithms turn into silicon-but keep an eye on hardware

So you have an algorithm or a compute-intensive function you want to implement in hardware. Does that mean you have to go through the traditional ASIC design flow, writing register-transfer-level VHDL ...
Electronic Design

Build Complex ASICs Without ASIC Design Expertise, Expensive Tools | Electronic Design

DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2. To implement custom digital logic for system-level prototyping and qualification, OEM system ...
Semiconductor Engineering

C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems ...