Design-Reuse

Designing low-power sequential circuits using clock gating

With shrinking technologies, rapid multiplication of clock frequencies, and increasing emphasis on power reduction, low-power design is taking on a vital role. Design teams can no longer afford to ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
EDN

SR Flip Flop Design with NOR Gate

Here is a simple circuit which helps to know how SR Flip Flop can be designed using NOR gate. In the circuit diagram, there are two input terminals S and R. The SR Flip Flop is one of the fundamental ...