Electronic Design

Extraction Tool Makes Grade On TSMC’s 45-nm Process

Cadence Design Systems’ QRC Extraction tool now handles parasitic extraction for designs targeted at TSMC’s 45-nm process technology. The 45-nm node presents typical advanced technology challenges, ...
Electronic Design

Q&A: A New Extraction Architecture Takes on Advanced-IC Challenges

This file type includes high resolution graphics and schematics when applicable. Carey Robertson, Director of Product Marketing, LVS and Extraction, Mentor Graphics Advanced IC processes require ...
EDN

Synopsys offers StarRC Custom extraction tool

MANHASSET, NY — Synopsys, Inc. has extended its Galaxy implementation platform with the StarRC Custom parasitic extraction solution for analog mixed-signal and custom digital IC design. StarRC ...
Semiconductor Engineering

High-Performance 5G IC Designs Need High-Performance Parasitic Extraction

We are rapidly approaching a future where 5G telecommunications will be the norm. With its increased data speeds and bandwidth, 5G has the potential to change the way we live our lives. But what does ...
Design-Reuse

Extraction Challenges Grow in Advanced Nanometer IC Design

Successive generations of foundry process technologies enable ever-increasing design density, performance, and power savings, if only designers can deal with growing challenges. Innovative new process ...
EDN

Upgraded tool speeds IC package analysis

SANTA CRUZ, Calif. — Promising an enhanced ability to model the electrical characteristics of IC packages, Fluent Inc. has rolled out Icemax 2.0. The new offering may help prevent some of the ...