Electronic Design

Q&A: A New Extraction Architecture Takes on Advanced-IC Challenges

This file type includes high resolution graphics and schematics when applicable. Carey Robertson, Director of Product Marketing, LVS and Extraction, Mentor Graphics Advanced IC processes require ...
EDN

Parasitic extraction must solve advanced node issues

Integrated circuit (IC) designers move to advanced process technology nodes to leverage higher performance, density, and functionality, as well as reduced delay and power consumption, enabled by ...
Electronic Design

Extraction Tool Makes Grade On TSMC’s 45-nm Process

Cadence Design Systems’ QRC Extraction tool now handles parasitic extraction for designs targeted at TSMC’s 45-nm process technology. The 45-nm node presents typical advanced technology challenges, ...
EDN

EDA start up rides ‘full wave’ of signal integrity

SANTA CRUZ, Calif. — Claiming a technology breakthrough with its full-wave 3D extraction technology, Optimal Corp. is gearing up to provide a suite of signal-integrity analysis solutions for chips, ...
Design-Reuse

Siemens collaborates with Samsung Foundry to expand 3D-IC enablement tools, optimize other EDA solutions for foundry's newest processes

June 12, 2024 -- Plano, Texas, USA -- Siemens Digital Industries Software today announced that, in collaboration with Samsung Foundry, they have developed compelling new capabilities for the ...
Semiconductor Engineering

Achieving Fast And Accurate Extraction Of 3D-IC Layout Structures

The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition to) ...