Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D ...

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Scan technology was developed as a structured test technique that divided the complex sequential nature of a design into small combinational logic blocks that could be tested individually. This added ...

With increasing numbers of ASICs finding their way into high-volume products, production testing of these devices must be fast, complete, trouble-free, and economical. To achieve these goals, ...