SAN MATEO, Calif. — To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line ...

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

HARDWARE DESIGN is a process of refining an idea from a highly abstract form to a concrete, physical implementation. Along the way, a design is continually transformed from a given state of ...

New design languages and new chips and systems mean a whole new set of design gotchas for today's developers. Once-simple tasks become difficult and, thankfully, once-difficult tasks become easy. This ...

The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical ...

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...