Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
•The final design for a 16-bit 3 number adder resulted in a worst-case propagation delay (tpd) of 22.017ns with Speculative execution and a group size of 4, an 18.5% improvement from 26.772ns, without ...
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