The shift to multi-die assemblies is forcing changes in how chips are tested and inspected in order to achieve sufficient yield ramp or respond more quickly to yield excursions.

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...

Test-flow partitioning between wafer sort and final package test can have a dramatic impact on the cost of test. In some cases, the migration of package tests can be done over time, but the test ...

GRENOBLE, France--(BUSINESS WIRE)--Hprobe, a provider of turnkey semiconductor Automatic Test Equipment (ATE) for magnetic devices, today announced a breakthrough magnetic test head revolutionizing ...

The back-end semiconductor manufacturing process refers to the IC packaging and testing that people often hear about. Specifically, the process known as chip probing (CP) is conducted to test the ...

The emergence of 3-D ICs presents test challenges that extend from design-for-test tools from design-automation companies to device handlers from equipment firms including Advantest and Multitest. A ...

Motorola Inc.’s semiconductor products sector (SPS) today said it has developed and qualified the first wafer level burn-in and test (WLBT) process for flip-chip microprocessors. Motorola aims to ...