EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.
Nature

Cache Performance and Memory Hierarchy Optimization

The dynamic interplay between processor speed and memory access times has rendered cache performance a critical determinant of computing efficiency. As modern systems increasingly rely on hierarchical ...

New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...
Semiconductor Engineering

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System

A technical paper titled “RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory” was published by researchers at ETH Zürich, KMUTNB, ...
Embedded

Understanding cache placement

In a computer, the entire memory can be separated into different levels based on access time and capacity. Figure 1 shows different levels in the memory hierarchy. Smaller and faster memories are kept ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...

SOCAMM2 Is The Memory Standard AI Is Looking For

AI infrastructure can't evolve as fast as model innovation. Memory architecture is one of the few levers capable of accelerating deployment cycles. Enter SOCAMM2 ...
PC World

How does CPU memory cache work?

In the eighties, computer processors became faster and faster, while memory access times stagnated and hindered additional performance increases. Something had to be done to speed up memory access and ...
EDN

Implementing DMA on ARM SMP Systems

This Application Note explores the implications associated with performing Direct Memory Access (DMA) operations on an ARM multi-core system such as the ARM11 MPCore and Cortex-A9 MPCore. The target ...
Semiconductor Engineering

AI Inference Needs A Mix-And-Match Memory Strategy

Interactive LLMs (chat, copilots, agents) with strict latency targets Long‑context reasoning (codebases, research, video) with massive KV (key value) cache footprints Ranking and recommendation models ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...