As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...

Recently, many methodologies have been introduced for reducing dynamic power for systems-on-chip (SoCs). These methodologies, however, impose restrictive physical constraints which have schedule ...

Deftly optimizing ASIC critical paths, this tool rides atop existing cell-based flows to improve timing while leaving physical design largely undisturbed. Timing closure for ASIC design has always ...

Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis. Most notably, it provides a more realistic estimation of timing relative ...

As feature sizes continue to shrink at a breakneck pace, transistor-level analysis and optimization in digital design is becoming a necessity for achieving a solution with the unique combination of ...

There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such ...

At its introduction almost three years ago, Zenasis Technologies' ZenTime was marketed as a standard cell-optimization tool largely for integrated device manufacturers (IDMs). But Zenasis has ...